Thyristors have been used by virtue of their low on-voltage characteristics as indispensable devices for large capacity power conversion, and GTO (gate turn-off) thyristors are used very often today in the high-voltage large-current range. Drawbacks of the GTO thyristors, however, have also become clear. For example, the GTO thyristors require a large gate current for turning-off, that is a turn-off gain of the GTO thyristors is small, and the GTO thyristors require large snubber circuits for their safe turning-off, etc. Furthermore, since the switching speed of the GTO is low, their use has been limited to the low frequency range. In 1984, V. A. K. Temple (cf. IEEE IEDM Tech. Dig., 1984, p282) disclosed a MOS control thyristor (hereinafter referred to as "MCT") which may be classified as a voltage driven type thyristor. Since then, analysis and improvement of the MCT have been done world wide. This is because the MCT is a voltage driven type thyristor which can be driven with a much simpler gate circuit than the GTO thyristors, and since the MCT turns on at low on-voltage. Recently, new device structures have been proposed which have two insulated gate structures and operate at a thyristor mode when the devices are turned on and at an IGBT mode when the devices are turned off (cf. S. Momota et al., Proceedings of IEEE ISPSD, '92(1992), p28, and Y. Seki et al., Proceedings of IEEE ISPSD, '93(1993), p159).
FIG. 8 is a cross section of a double insulated gate MOS device (DGMOS) disclosed in 1992. In FIG. 8, the device has a p.sup.+ collector layer 21 on which is formed an n.sup.- layer 23 via an n.sup.+ buffer layer 22. A p type base region 24 is selectively formed in the surface layer of the n.sup.- layer 23. In the surface layer of the p type base region 24, n type base regions 25 are selectively formed. P type emitter regions 26, 26 are also selectively formed in the surface layer of each n type base region 25. An emitter electrode 27 is fixed commonly to the p type emitter regions 26 and n type base region 25. The emitter electrodes 27 are connected to the emitter terminals E. The first gate electrode 31 is fixed via a gate oxide film 28 to the exposed area of the n.sup.- layer 23, the portion of the p type base region 24 extending between the n.sup.- layer 23 and the n type base region 25, and the portion of the n type base region 25 extending between the p type base region 24 and the emitter region 26. The first gate electrode 31 is covered with an insulation film 29, and connected to the first gate terminal G1 through the opening of the insulation film 29. The second gate electrode 32 is fixed via the gate oxide film 28 to the portion of the p base region 24 extending between the n type base regions 25 and the portions of the n type base regions 25 extending between the p base region 24 and the p type emitter region 26. The second gate electrode 32 is covered with the insulation film 29, and connected to the second gate terminal G2 through the opening of the insulation film 29. A collector electrode 30 is fixed to the p.sup.+ collector layer 21, and connected with a collector terminal C.
Voltages are applied to the first and second gate electrodes 31 and 32 in a manner as shown in FIG. 9. When a voltage exceeding the threshold value is applied to the terminal G1, an inversion layer is formed in the surface region of the p type base region 24 below the first gate electrode 31. As electrons pass through the inversion layer, an electron current flows into the n.sup.- layer 23 and the n.sup.+ buffer layer 22. Since a positive voltage is applied to the collector electrode 30, the current which has flowed into the n.sup.- layer 23 and the n.sup.+ buffer layer 22 generates a base current of a built-in PNP transistor consisted of the p.sup.+ collector layer 21, the n.sup.+ buffer layer 22 and the n.sup.- layer 23, and the p type base region 24. The base current modulates the conductivity of the n.sup.- layer 23 and turns on the PNP transistor. A hole current caused by the conductivity modulation generates a base current of a built-in NPN transistor consisted of the n.sup.+ buffer layer 22 and the n.sup.- layer 23, the p type base region 24, and the n type base region 25. The base current drives the NPN transistor to finally operates a PNPN transistor consisted of the p+ collector layer 21, the n.sup.+ buffer layer 22 and the n.sup.- layer 23, the p type base region 24, and the n type base region 25. Thus, the DGMOS of FIG. 8 is turned on through the terminal G1.
The DGMOS of FIG. 8 is turned off by removing the gate voltages applied to the gate electrodes 31 and 32 with a time lag as shown in FIG. 9. The voltage of the second gate electrode 32 grounded at the time t1 becomes negative with respect to the voltage of the gate electrode 31. As a result, an inversion layer is formed in the surface layer of the n type region 25 below the second gate electrode 32, and a p-channel MOSFET is turned on. Since the turning-on of the p-channel MOSFET causes short-circuit of the p type base region 24 and the n type base region 25, the basic structure becomes equivalent to an IGBT. Therefore, in steady state operation, the DGMOS operates in the thyristor mode through the first gate electrode 31. The DGMOS shifts to the on-state of the IGBT operation mode at the time t1 at the start of turning-off in response to negatively biassing the second gate electrode 32 with respect to the first gate electrode 31. At the time t2, 3 to 4 .mu.sec after the IGBT operation mode starts, the DGMOS is turned off by removing the voltage applied to the first gate electrode 31 to stop the electron supply.
The device disclosed in 1993 (DGMOT) has had its on-resistance lowered by converting the p-channel device of FIG. 8 to an n-channel one. These devices are characterized by the above-described mode switching which realizes in one single device the low on-resistance of the thyristor and high speed switching of the IGBT.
However, the uneven operations inside the MCTs and the devices having two insulated gate structures suppress the maximum controllable current at such small values that these devices can not practically be used.
In view of the foregoing, it is an object of the present invention to provide an insulated gate thyristor which facilitates controlling a large current.